| 摘要 |
An ECL/CML to TTL translator circuit couples the output of an ECL/CML gate to the input of a TTL gate. The ECL/CML gate operates with reference to a first power rail higher reference voltage level with transistor elements operating in the non-saturation operating region. The TTL gate operates with reference to a second power rail lower reference voltage level with transistor elements operating in the saturation threshold operating region. The translator circuit includes a reference voltage level shifting constant current non-switching current mirror circuit coupled to the output of the ECL/CML gate for shifting the reference voltage level of the ECL/CML gate output from the higher reference voltage level to the lower reference voltage level. An operating region translating emitter follower output buffer circuit is coupled to receive the voltage level shifted output signal and drive the input of the TTL gate. The circuit functions of reference voltage level shifting and of operating region translating are thereby separated. Base drive to the phase splitter transistor element is limited by a base drive limiting anti-saturation clamp circuit. More generally, an overdrive and anti-saturation clamp control circuit provides high speed switching of a phase splitter transistor element, pulldown transistor element, or other TTL switching transistor element for generalized application in TTL internal and output gates and buffers. The overdrive and clamp control circuit provides a "programmable" base-collector clamp voltage for operation of TTL switching transistor elements in "soft" saturation, in threshold saturation, or entirely out of saturation for operation of linear TTL circuits.
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