| 摘要 |
The circuit makes it possible to control the length of the processed operand, the latter being translated by a decoder (20) into a sequence of bits corresponding respectively to the various decimal digits of this operand, each bit having a first value indicating the validity of the corresponding decimal digit and a second value indicating the non-validity of the corresponding decimal digit. The bits corresponding to the decimal digits with odd-numbered place are inverted by invertors (22 to 25) and applied to first equivalence gates (26 to 29) so as to detect an equivalence with respective bits which correspond to the decimal digits with even-numbered place. The presence of a non-zero bit in each of the decimal digits with odd-numbered place is detected by absence-of-zero detectors (31 to 34) and provided to second equivalence gates (35 to 38) so as to detect an equivalence with the output signals from the first equivalence gates, so as to generate a signal indicating an exception event. …<??>Application to data processors. … <IMAGE> … |
