| 摘要 |
<p>An integrated circuit chip carrier having reduced and predictable interlead capacitance, reduced glass chip formation, and improved wirebonding characteristics is disclosed. The chip carrier includes a substrate (201) having a central cavity (106) for locating an integrated circuit die, an inner channel (202) and an outer channel (203), adhesive glass (105) located in the channels and overflowing above the substrate surface, a leadframe mounted on the substrate having a plurality of leads (107) embedded in the adhesive glass overflow and coplanarly resting on the substrate, the leads extending from beyond the substrate periphery inward to near the cavity rim, and a thin layer of sealing glass (104) extending from the periphery of the substrate over the outer channel for hermetically sealing the chip carrier.</p> |
