A microcomputer and a method for controlling its bus cycle.

摘要

A microprocessor processes ordinary operations in a predetermined bus cycle when a wait trigger condition of a wait request signal inputted from a wait request signal creating means (105) provided outside of the microprocessor (101) is detected. The bus cycles in the microprocessor (101) are caused to wait for a predetermined wait period thereafter in the microprocessor (101). After the predetermined wait period has elapsed, the wait is cleared to return the microprocessor (101) to the original bus cycle. <IMAGE> <IMAGE> <IMAGE>