发明名称 |
Method and apparatus for bit operational process |
摘要 |
A bit operation processor having a first address operation unit for updating the address of data in units of a byte or multiple bytes for performing operation in units of a byte or multiple bytes. A second address operation unit for updating the address of data in units of a bit or multiple bits, an address controller operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit. Fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.
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申请公布号 |
US5034900(A) |
申请公布日期 |
1991.07.23 |
申请号 |
US19850779794 |
申请日期 |
1985.09.24 |
申请人 |
HITACHI, LTD. |
发明人 |
KIMURA, KOICHI;OGURA, TOSHIHIKO;AOTSU, HIROAKI;URABE, KIICHIRO |
分类号 |
G06F7/00;G06F3/153;G06F9/308 |
主分类号 |
G06F7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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