| 摘要 |
2086229 9200563 PCTABS00010 This invention relates to the generation of number theory mappings and their application to the addressing of matrix structures through the provision of an address generator which is optimised for the general task of applying "on the fly" number theory mappings to matrix operands as they are fetched from memory. The address generator (10) comprises a set of six matrix descriptor storage registers (11-16), a finite state machine controller (17), a decrementer (18) for cyclically decrementing a matrix size descriptor (12), an additional decrementer (19) for cyclically decrementing the matrix size descriptor (11), a finite difference engine (20) which adds one of two matrix difference descriptors (13 or 14) to a previously calculated address value obtained from the address register (21), a modulo arithmetic computation unit (22) which computes the residue of the finite difference engine output (20) modulo, the matrix modulo descriptor (15) and an adder (23) which adds an offset value stored as the matrix base descriptor (16) to the output of the modulo arithmetic computation unit (22). The output sequence from the base adder (23) is the desired address generator output.
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