| 摘要 |
<p>A cache controller (16) for a set associative cache memory (46) seletively remaps predetermined bits (a12-a15) of the cache address so as to confine data from a single memory page to a particular block of the cache memory (46). When changing a memory page, only the particular block of the cache in which data from that page may be stored is flushed, thereby preserving the remaining contents of the cache.</p> |
