| 摘要 |
A CPU (1) is connected through address lines (AL) to a chip selecting logic (14), a device selecting logic (2), a RAM (3), a program ROM (4) and comparing ROMs (5,6), while the CPU (1) is also connected through data lines (DL) to buffers (7,8) and to the program ROM (4). The chip selecting logic (14) and a data selecting logic (15) are connected through a data line (D7) to the CPU (1). Read/write signals and RAM chip selecting signals are supplied to the device selecting logic (2), while program chip selecting signals are also supplied to the device selecting logic (2). Enable signals are supplied to the buffers (7,8), and signals from the ROM chip selecting logic (14) are supplied to the comparing ROMs (5,6). With the circuit, the memory data can be automatically compared.
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