The circuit comprises at least one diode and has a parallel connection of a limiting diode (D1) and a capacitor (C1), in front of which is series-connected a diode (D2). Pref. a similar arrangement of a limiting diode (D3) with a parallel connected capacitor (C3) and further diode (D4) is provided. The additional limiting diode and the further diode are in anti-parallel to the first arrangement of the limiting diode and its series-connected diode. The limiting diodes are typically Zener diodes. The additional diodes may form a series connection. The capacitors may be chip components. A level monitoring signal may be tapped at each capacitor.
申请公布号
DE3685595(D1)
申请公布日期
1992.07.16
申请号
DE19863685595
申请日期
1986.02.25
申请人
PHILIPS PATENTVERWALTUNG GMBH, 2000 HAMBURG, DE
发明人
HABERDITZL, DIPL.-ING. (FH), RAINER, W-8500 NUERNBERG, DE