发明名称 |
CIRCUIT ARRANGEMENT FOR AVERAGING IN THE PULSE DENSITY D/A OR A/D CONVERSION |
摘要 |
<p>In the pulse density D/A or A/D conversion, an improved averaging of a PDM signal (pm) in a jittering clock signal (cl) is achieved by the fact that the PDM signal (pm) is supplied to the series input (zs) of an n-stage shift register (sr), the parallel output (z1, ...zn) of which is used for controlling n state signals (i4....;ii'....; i8....; i8d), the shift register (sr) being switched by the clock signal (cl). The n state signals are combined to form a sum signal (i4s; i6s; i8s; si, siq) which feeds a low-pass filter (tp). Particularly advantageous developments are obtained if the n state signals are weighted and/or isolated from the respective preceding and subsequent state in time by means of gate circuits (g; g, gs). …<IMAGE>… </p> |
申请公布号 |
EP0335988(B1) |
申请公布日期 |
1992.12.23 |
申请号 |
EP19880105242 |
申请日期 |
1988.03.31 |
申请人 |
DEUTSCHE ITT INDUSTRIES GMBH |
发明人 |
PFEIFER, HEINRICH, DIPL.-ING.;REICH, WERNER, DR.;THEUS, ULRICH, DR. |
分类号 |
H03M1/60;H03M3/04 |
主分类号 |
H03M1/60 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|