Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement

摘要

A plurality of memory arrays (10a, 10b) are formed on a semiconductor chip (CH). A peripheral circuit (60) is arranged in the central portion of the plurality of memory arrays (10a, 10b). A plurality of pads (PD;p1 DIFFERENCE p18) are formed on both ends of the semiconductor chip (CH). The plurality of memory arrays (10a, 10b) are formed of predetermined layers (101 DIFFERENCE 109). A plurality of interconnections (L) to be connected between the plurality of pads (PD;p1 DIFFERENCE p18) and the peripheral circuit (60) are provided to cross the plurality of memory arrays. The plurality of interconnections (L) are formed of layers (112;113) other than the predetermined ones.