Solid state memory with block selection circuit - uses address signals received by AND gate logic to generate signals to select and activate logic blocks

摘要

The solid state memory is formed in a number of main blocks (ULA, URA, LLA, LRA) that are each subdivided into a number of sub-blocks that are separately activated. Block selectors (31-34) use line and column address signals to identify specific locations. The line address signals are tied to specific inputs of AND gates (31), such that combinations may be used to identify specific memory blocks. Once selected, the column address signals may be used to identify locations within the blocks. ADVANTAGE - Reduced power requirement for memory access logic.