发明名称 MULTI-LINK CONTROL SYSTEM
摘要 PURPOSE:To use a multi-link procedure with a line configuration for which a delay and a profltability are considered. CONSTITUTION:A through put value memory 301 stores the quantity of transmission and reception data between multi-links in a multi-link procedure counted and stored by a quantity of transmission and reception data counter memory 300. A line quality value memory 201 stores the number of times of error each line counted and stored by an error counter memory 200. Based on the data stored in the through put value memories 301, 302 and the line quality value memory 201, an optimum line constitution is selected from multi- link lines 100, 101, 102, the data transmission and reception ratio of each line is stored in a data transmission ratio memory 400 and a packet switchboard A performs a multi-link control in accordance with this transmission and reception ratio and the selected circuitry.
申请公布号 JPH0595373(A) 申请公布日期 1993.04.16
申请号 JP19910253299 申请日期 1991.10.01
申请人 NEC CORP;NEC ENG LTD 发明人 IBATA MITSUNORI;SHIINA YUTAKA
分类号 H04L12/56 主分类号 H04L12/56
代理机构 代理人
主权项
地址