| 摘要 |
<p>A compensated digital delay semiconductor device is disclosed which uses two identical chains (10 and 12) of delay elements (14). The first chain is the Reference Chain (10), which is driven by a crystal-controlled digital clock input (17). The second chain is the Input Signal Delay Chain (12), which is the delay path for the signal of interest. These two chains (10 and 12) are located in physical proximity on the semiconductor die so that variations in the manufacturing process, temperature and power supply affect each chain (10 and 12) the same. Circuitry monitors the delay performance of the Reference Chain (10), and dynamically changes the output tap (40, 42, 44, 46, 48, 50, 52, and 54) of the Input Signal Delay Chain (12) when a change in performance is detected on the Reference Chain (10), thereby compensating the delay of the device. This approach provides precise delays which are constant.</p> |
