DUAL-WRITING DEVICE AND METHOD USING LATCHES

摘要

The data, the address, and the control signal of a processor are latched until a write mode of an other side processor is completed and a process cycle is quitted when a write mode of a processor is completed so that the time necessary to write data on a memory is shortened. The apparatus includes an address decoder (44) for decoding an address signal transmitted through an internal bus (51) an MPS bus interface (46) for interfacing an internal bus and an MPS bus, an error decoder (52) connected to a processor (43), the internal memory (45) and the MPS bus interface (46), and an address latch (64) connected to the internal bus (51) and the error decoder (52) to latch an address and an error signal when an error occurs in the MPS bus interface (46) and the memory on the other side.