发明名称 |
Switch-level timing simulation based on two-connected components |
摘要 |
A method for simulating a transistor circuit determines which nodes in the circuit change state in response to events, and then accurately computes the times at which those nodes change states. Using parasitic capacitance and transistor conductance values extracted from the circuit layout, this method and evaluates driving-point resistances and delays in an RC-network representation of the complete circuit.
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申请公布号 |
US5305229(A) |
申请公布日期 |
1994.04.19 |
申请号 |
US19910756078 |
申请日期 |
1991.09.06 |
申请人 |
BELL COMMUNICATIONS RESEARCH, INC. |
发明人 |
DHAR, SANJAY |
分类号 |
G06F17/50;(IPC1-7):G06F15/20 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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