发明名称 Semiconductor wafer and method for manufacturing semiconductor device
摘要 A semiconductor wafer including patterns transferred to a plurality of shot regions of the semiconductor wafer respectively, a plurality of chip regions being formed in the plurality of shot regions respectively, a plurality of first dummy patterns being formed respectively in a first chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of first dummy patterns being arranged repeatedly in a first manner, a plurality of second dummy patterns being formed respectively in a second chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of second dummy patterns being arranged repeatedly in a second manner different from the first manner.
申请公布号 US9508559(B2) 申请公布日期 2016.11.29
申请号 US201314030662 申请日期 2013.09.18
申请人 FUJITSU SEMICONDUCTOR LIMITED 发明人 Saito Shoko;Okada Tomoyuki;Takeuchi Kanji;Naoe Mitsufumi;Minemura Masahiko;Sato Yukihiro;Konno Yoshito;Inada Yasuhiko;Inaoka Tomoaki;Sashida Naoya
分类号 G01R31/28;H01L29/00;H01L21/308;H01L21/3213;H01L23/544;H01L23/522;H01L23/00 主分类号 G01R31/28
代理机构 Westerman, Hattori, Daniels & Adrian, LLP 代理人 Westerman, Hattori, Daniels & Adrian, LLP
主权项 1. A semiconductor wafer comprising: patterns transferred to a plurality of shot regions of the semiconductor wafer respectively, a plurality of chip regions being formed in the plurality of shot regions respectively, the plurality of chip regions including first chip regions functioning as ordinary semiconductor chips and a second chip region functioning as a semiconductor chip used as a mark, the second chip region being provided one for each of the plurality of shot regions, the plurality of chips regions other than the second chip region being the first chip regions, a plurality of first dummy patterns being formed respectively in the first chip region, the plurality of first dummy patterns being arranged repeatedly in a first manner, the first dummy patterns being not electrically connected to any interconnection layers, a plurality of second dummy patterns being formed respectively in the second chip region, the plurality of second dummy patterns being arranged repeatedly in a second manner different from the first manner, the second dummy patterns being not electrically connected to any interconnection layers.
地址 Yokohama JP
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