| 摘要 |
An integrated circuit system comprising a first chip including a first period signal generation unit configured to generate a first period signal, transmit a first signal applied from a circuit outside of the integrated circuit system to a second chip, and transmit a second signal transmitted from the second chip to the circuit outside of the integrated circuit system, and the second chip including a second period signal generation unit configured to generate a second period signal, a code generation unit configured to generate codes corresponding to a difference between periods of the first period signal and the second period signal, and a delay unit configured to delay the second signal by using a delay value that is changed according to the codes. |
| 主权项 |
1. An integrated circuit system comprising:
a first chip including a first period signal generation unit configured to generate a first period signal, the first chip configured to transmit a first signal applied from a circuit outside of the integrated circuit system to a second chip and transmit a second signal transmitted from the second chip to the circuit outside of the integrated circuit system, wherein the first period signal has a period corresponding to an operation speed of the first chip that changes depending upon process, voltage and temperatures (PVT) conditions of the first chip: and the second chip including a second period signal generation unit configured to generate a second period signal, a code generation unit configured to generate a code corresponding to a difference between the period of the first period signal and a period of the second period signal, and an output control unit configured to transmit the second signal to the first chip at a time that is determined according to the code, wherein the second period signal has the period corresponding to an operation speed of the second chip that changes depending upon the PVT conditions of the second chip, wherein the code is generated based on a difference between a value obtained by counting a reference clock during an interval corresponding to the first period signal and a value obtained by counting the reference clock during an interval corresponding to the second period signal, wherein the first chip and the second chip are stacked, and the PVT conditions of the first chip are different from the PVT conditions of the second chip, wherein the output control unit comprises a strobe section configured to transmit the second signal to the first chip at a time when a strobe signal is activated and a delay line configured to control a delay value of the strobe signal according to the code, wherein the delay line comprises a plurality of asynchronous delay sections that are activated or deactivated in response to the code, and wherein the plurality of asynchronous delay sections delay a signal without being synchronized with a clock. |
