| 摘要 |
PCT No. PCT/JP91/01272 Sec. 371 Date Mar. 25, 1993 Sec. 102(e) Date Mar. 25, 1993 PCT Filed Sep. 25, 1991 PCT Pub. No. WO92/05560 PCT Pub. Date Apr. 2, 1992.A memory cell array is divided into a plurality of blocks. In altering data for a block (selected block), a moderating voltage is applied to the source or control gate of a memory cell in another block (non-selected block) to moderate stress between the floating gate and source/drain, thereby preventing write error and erase error. In the program operation, the source and drain of a memory cell in the non-selected block are equalized to moderate an electric field between the control gate and source/drain and not to flow a channel current, thereby preventing write error. In carrying out a negative voltage erase method, prior to setting the source line and word line of a cell in a non-selected block to an erase voltage, the source and word lines are equalized. The equalization operation is released after the erase operation, thereby preventing malfunction of a non-selected cell.
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