| 摘要 |
The decoder decreases the hardware processing speed and saves the memory capacity. The decoder comprises; an interface unit (1) generating the code word windows (I0-I7) so that the input signal (Vi) is shifted by accumulation of the word length (L0-L2); a word length detector (2) outputting code word length information according to the output of the interface unit; a decoder unit (3) outputting the original information (V0-V2) corresponding to the interface output; a barrel shifter (20) forming windows (I0-I7); an adder (60) outputting the total (S0) and carry (C0); a latch uni t(70) holding up the carry (C0) according to the ready signal (RDY); a read signal generation unit (80) outputting the read signal (RD) to the latch unit.
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