One bit error correction method having actual data reproduction function
摘要
A 1-bit error correction circuit based on CRC calculation is provided with a syndrome generation circuit which determines input parallel data of m bits and which have been converted from n number of m-bit serial data. A 1-bit error detection circuit cyclically supplies a syndrome to a remainder calculation circuit and decodes remainder data obtained from this cyclic supply and detects 1-bit errors. A actual data reproduction circuit calculates the exclusive OR of output data of a predetermined register of a 1'st DIFFERENCE n'th register of a syndrome generation circuit and data supplied to a predetermined register and obtains parallel data which is the actual data. A correction circuit which calculates a exclusive OR of parallel data obtained from a actual data reproduction circuit and 1-bit error data detected by the 1-bit error detection circuit and outputs corrected data.
申请公布号
US5408476(A)
申请公布日期
1995.04.18
申请号
US19930016871
申请日期
1993.02.11
申请人
FUJITSU LIMITED;NIPPON TELEGRAPH AND TELEPHONE CORPORATION