Semiconductor memory device having a memory cell unit including a plurality of transistors connected in series

摘要

A semiconductor memory device comprising a memory cell array having a plurality of dynamic memory cells, each of the memory cells including a plurality of MOS transistors connected by cascade connection, capacitors for storing data each having an end connected to an end of a corresponding one of the MOS transistors, and a register arranged in a column portion of the memory cell array, for temporarily registering the data read from the memory cells in a time series manner.