A semiconductor memory device includes a memory cell array (10) having a plurality of memory cells (MC) and formed by a mask ROM, the memory cell array having a data area (10a) in which data (SO1 - SO16) of n bits (n is an arbitrary number) is stored and a parity area (10b) in which a one-bit parity code (Pb) relating to the data is stored. A control circuit (13, 14) supplies the memory cell array with an address and reads out the data and the one-bit parity code designated by the address. A parity check circuit (16) determines whether or not the data read out from the memory cell array has a bit error and generates correction data (CB) indicating a determination result. A memory (17) stores defective output indicating data (S1 - S16) indicating one of the n bits of the data having the bit error. A data correction circuit (15) corrects one of the n bits of the data indicated by the defective output indicating data by the correction bit.
