Digital PLL circuit having signal edge position measurement

摘要

A ring oscillator has its inverter states in respective inner stages change at a time unit longer than a period of a master clock MCK and is oscillated at a period longer than the period of the master clock MCK. The inverter states of the respective stages of the ring oscillator are captured by a flipflop circuit and a value indicating each of these states is subtracted by a subtractor from numerical figures indicating the inverter states in the respective stages of the ring oscillator as captured at the timing of the master clock MCK by other flipflop circuits. The difference is output as a signal indicating the position of the input signal edge.