| 摘要 |
A method and apparatus are provided for performing a Hadamard transform operation. The basic building block of the apparatus is an FHT engine having a difference circuit for subtracting the input symbol from a delayed processed symbol, first multiplexer for providing either the difference of the delayed processed symbol and the input symbol or the input symbol, a summing circuit for adding the input symbol to the delayed processed symbol and a second multiplexer for providing either the sum of the input and the delayed processed symbol or the delayed processed symbol as an output. This basic engine is designed to work in conjunction with a variety of different memory configurations. The engines can then be placed in series to perform a Hadamard transform of all defined orders. In addition, two methods of optimizing the use of memory resources are described. On involves the optimal configuration of the memory elements and the second involves truncation. Also, provided is a method and apparatus for performing the transform on samples provided as a serial bit stream to the apparatus. |
