发明名称 Instruction and Logic for a Convertible Innovation and Debug Engine
摘要 A processor includes an innovation engine, a non-volatile memory, a reserved device, one or more user-defined devices, and logic to execute the user-defined devices. The processor also includes a debug engine with logic to monitor the processor for trigger conditions and record data associated with the trigger conditions. The innovation further includes logic to selectively load the debug engine.
申请公布号 US2016283351(A1) 申请公布日期 2016.09.29
申请号 US201514671541 申请日期 2015.03.27
申请人 Huang Sheng S. 发明人 Huang Sheng S.
分类号 G06F11/36 主分类号 G06F11/36
代理机构 代理人
主权项 1. A processor, comprising: an innovation engine including a memory, a reserved device, one or more user-defined devices to modify functionality of the processor, and logic to execute the user-defined devices and the reserved device; and a debug engine including: a first logic to monitor the processor for trigger conditions; anda second logic to record data associated with the trigger conditions; wherein the innovation engine further includes a third logic to selectively launch the debug engine.
地址 Folsom CA US