发明名称 UV-CURE PRE-TREATMENT OF CARRIER FILM FOR WAFER DICING USING HYBRID LASER SCRIBING AND PLASMA ETCH APPROACH
摘要 Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits on a front side of the semiconductor wafer includes adhering a back side the semiconductor wafer on the dicing tape of a substrate carrier. Subsequent to adhering the semiconductor wafer on a dicing tape, the dicing tape is treated with a UV-cure process. Subsequent to treating the dicing tape with the UV-cure process, a dicing mask is formed on the front side of the semiconductor wafer, the dicing mask covering and protecting the integrated circuits. The dicing mask is patterned with a laser scribing process to provide gaps in the dicing mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the dicing mask layer to singulate the integrated circuits.
申请公布号 US2016315009(A1) 申请公布日期 2016.10.27
申请号 US201514697391 申请日期 2015.04.27
申请人 Lei Wei-Sheng;Eaton Brad;Park Jungrae;Kumar Ajay;Papanu James S.;Kumar Prabhat 发明人 Lei Wei-Sheng;Eaton Brad;Park Jungrae;Kumar Ajay;Papanu James S.;Kumar Prabhat
分类号 H01L21/78;H01L21/683;H01L21/268;H01L21/67;H01L21/308;H01L21/3065 主分类号 H01L21/78
代理机构 代理人
主权项 1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits on a front side of the semiconductor wafer, the method comprising: adhering a back side the semiconductor wafer on the dicing tape of a substrate carrier; subsequent to adhering the semiconductor wafer on a dicing tape, treating the dicing tape with a UV-cure process; subsequent to treating the dicing tape with the UV-cure process, forming a dicing mask on the front side of the semiconductor wafer, the dicing mask covering and protecting the integrated circuits; patterning the dicing mask with a laser scribing process to provide gaps in the dicing mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits; and plasma etching the semiconductor wafer through the gaps in the dicing mask layer to singulate the integrated circuits.
地址 San Jose CA US