Test pattern generator

摘要

A test pattern generator accompanying digital integrated circuits for successively generating a plurality of test patterns for a built-in self test. A plurality of shift registers are serially connected in a loop for successively outputting the test patterns in response to a clock signal. At least one logic gate is connected among the shift registers. At least one control means is connected within the loop. Using such a configuration, the shift registers are set to an initial pattern. The shift registers are then set to one of a plurality of test patterns. The test patterns are then successively output through the shift registers in response to the clock signal.