| 摘要 |
A pseudo random noise sequence code generating circuit comprises: a sequence generating means (11) for sequentially generating a maximum length linear code sequence at an N-chip cycle; and the first to the (N-1)th vector multiplying means (12 to 14) for obtaining values of skipped portions in the sequence generating means respectively by vector multiplication, on the basis of the state value (S1) of a register forming the sequence generating means, and generates a successive pseudo random noise sequence code based on an output of the sequence generating means (PN1) and outputs of the first to the (N-1)th vector multiplying means (PN2 to PN4). Thereby, the operating rate can be reduced to 1/N comparing with a prior art; the operating voltage can be reduced, and lowering the electric power consumption. |
