| 摘要 |
A system for inhibiting interrupts during posted write transfers in a computer system utilizes a buffer to store incoming data and addresses while monitoring incoming addresses to determine if the address is an Input/Output reference to an interrupt controller. If an Input/Output reference to an interrupt controller is detected, a counter is incremented which outputs a logical zero output. A signal indicating a counter value of zero is provided as an input to an AND gate. A second input to the AND gate is provided from an interrupt controller. When the counter contains a non-zero value, a zero input is provided to the AND gate and a zero output is provided to the system bus, regardless of the output from the interrupt controller, inhibiting all further interrupts. Thus, when an interrupt mask is set by a CPU, the present invention immediately inhibits further interrupts from occurring, thereby permitting processing to continue without interruption. As a result, processing time is increased.
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