Transition rate controlled bus driver circuit with reduced load sensitivity

摘要

A bus driver circuit (FIG. 2) is disclosed. The circuit includes a signal lead of a bus (200) and a reference terminal (Vss). A first transistor (MN0) has a first control terminal and has a first current path coupled to the reference terminal. A second transistor (MN1) has a second control terminal coupled to the first control terminal and has a second current path coupled between the signal lead and the reference terminal. A third transistor (MP0) is arranged to provide a first current through the first current path when the signal lead is in a first logic state (high). A fourth transistor (MP1) is arranged to apply a voltage to the second control terminal when the signal lead is in a second logic state (low).

主权项

1. A circuit, comprising:
a signal lead; a reference terminal; a first transistor having a first control terminal and having a first current path coupled to the reference terminal; a second transistor having a second control terminal coupled to the first control terminal and having a second current path coupled between the signal lead and the reference terminal; a third transistor arranged to provide a first current through the first current path when the signal lead is in a first logic state; and a fourth transistor arranged to apply a voltage to the second control terminal when the signal lead is in a second logic state.