| 摘要 |
The timings can be generated in synchronism with master clocks, so that it is possible to obtain the timing generating device of synchronous circuit, which is effectively applicable to a large scale integrated circuit, while facilitating the test thereof. Addresses A [0, m-1] are given to the register 1 in synchronism with the input pulses CLK; delay data D [0, n-1] are read from the memory device 3 on the basis of the outputs of the register 1; the delayed data are stored in the registers 4-1 to 4-k independently on the basis of the distributive pulses CK1 to CKk applied by the pulse distributing circuit 2 for distributing the input pulse CLK to a plurality of routes in sequence; the data signals S1i to Ski obtained by the registers 4-1 to 4-k are given to the delay circuits 6-1 to 6-k through the DA converters 5-1 to 5-k to control the delay times in such a way that the distributive pulses CK1 to CKk can be controllably delayed by the delay circuits 6-1 to 6-k; and the obtained delay pulses CK1X to CKkX are outputted through the OR gate 7 as a continuous pulse train.
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