| 摘要 |
A line length extracting means (2) establishes a correspondence between line length data extracted from layout data (D2) and output lines in an LSI circuit specified by LSI circuit connection data (D1), respectively, to output line length data (D5) to a model selecting means (3), which in turn compares the total line length of each output line (output signal) with a predetermined reference line length (SL) on the basis of the line length data (D5) and selects an RC model for the output line having the total line length greater than the reference line length (SL) and a C model for the output line having the total line length less than the reference line length (SL) to output a model selection result (D6) in which selected model names correspond to output signal names to a wiring delay element inserting means (4), whereby a device and method for calculating an accurate delay time at high speeds is provided.
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