| 摘要 |
An automatic testing circuit where, according to the once test command, generates the address signal in order in the inner of memory element and performs the operation of the write and read. The said circuit consists of a test command signal generating means that the test command signal according to input the row address strobe signal, column address strobe signal, write signal, and read signal; a row address signal generating means that generates the row address signal according to the test command signal from the test command signal generating means and the row address strobe signal from outside; and a column address signal generating means that generates the column address signal according to the test command signal from the test command signal generating means and the clock signal of the constant frequency.
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