发明名称 WIRING STRUCTURE OF INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To prevent the influence of TiW on grain size by placing a Pt layer of a specified thickness between a TiW layer and an Au layer of specified thickness. SOLUTION: An active layer 2 and a n<+> -layer 3 are formed on a semi- insulating GaAs substrate 1, and Si ions are implanted therein. Activation is performed by annealing, and then electrodes of gate 4, source 5, and drain 6 are formed to complete FET. A TiW layer 11 as lower metal, a Pt layer 12 and an Au layer 13 are continuously formed in this order by sputtering. The thickness of the Pt layer is from 50Åto 300Åinclusive. The thickness of the TiW layer is from 50Åto 500Åinclusive. These layers 11, 12, 13 are removed by ion milling, and then a TiW layer 21, a Pt layer 22, and an Au layer 23 are formed as a second wiring layer. This makes it possible to prevent increase in the grain size of Au, and to significantly reduce variation in resistance value even after a long-term energizing test.
申请公布号 JPH09246268(A) 申请公布日期 1997.09.19
申请号 JP19960052944 申请日期 1996.03.11
申请人 SUMITOMO ELECTRIC IND LTD 发明人 ISHII MANABU
分类号 H01L21/28;H01L21/3205;H01L23/52;(IPC1-7):H01L21/320 主分类号 H01L21/28
代理机构 代理人
主权项
地址
您可能感兴趣的专利