发明名称 Voltage generation circuit with output fluctuation suppression
摘要 An NMOS transistor (2) has a source electrode, a drain electrode and a gate electrode which are connected to a power source (VSS), an output terminal of a stepdown circuit (27), and a node (N2) between load elements (11, 12) respectively. The transistor size of the NMOS transistor (2) is so set that its drain current exerts no influence on fluctuation of an output voltage (VDD2) when an output voltage control operation by a differential amplification circuit (29) and the stepdown circuit (27) is functional to enable suppression of fluctuation of the output voltage (VDD2), while the output voltage (VDD2) is stepped down on the basis of the current quantity of the drain current of the NMOS transistor (2) when the output voltage control operation is unfunctional to disable suppression of fluctuation of the output voltage (VDD2). Thus, obtained is a voltage generation circuit which can reliably suppress fluctuation of the output voltage regardless of the frequency of fluctuation in source voltage.
申请公布号 US5694076(A) 申请公布日期 1997.12.02
申请号 US19960622269 申请日期 1996.03.27
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 ISHIBASHI, ATSUHIKO
分类号 H03K19/00;G05F1/46;H03F3/45;(IPC1-7):G05F1/10 主分类号 H03K19/00
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