| 摘要 |
PROBLEM TO BE SOLVED: To exactly find circuit delay in a short time in optimizing processing of a logic circuit at a technology notdepending level. SOLUTION: While paying attention onto one path a→b→c→d→e in an object circuit, this path is mapped by library cells ao 21 and aoi 21 having the same path pattern. Then, the delay of path a→b inside the cell ao 21 is added with the delay of path c→d→e inside the cell aoi 21 and the delay of path a→b→c→d→e is found. The existence of consistency between such path mapping and technology mapping is shown and high-accuracy delay value is found. Besides, since mapping is performed while paying attention only upon the path, this mapping is extremely accelerated rather than technology mapping.
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