发明名称 Integrated circuit multi-level interconnection technique
摘要 An improved integrated circuit conductor layout technique provides lower and upper conductor levels (209'-212'; 209-212) that bound circuit blocks (201, 206, 207 and 208) and provide for power supply voltage distribution to the circuitry in the circuit blocks. The lower and upper conductor levels also provide for first (301, 304, 305, 308) and second (306, 307) groups of parallel signal conductors in wiring channels between circuit blocks. An intermediate conductor level is located between the lower and upper conductor levels, and conducts power supply voltages (VDD, VSS) between adjacent circuit blocks. The power supply conductors (217-222) formed in the intermediate conductor level also serve to isolate the signal conductors in the lower conductor level (301', 304', 305', 306', 307', 308') from the signal conductors in the upper conductor level (301, 304, 305, 306, 307, 308) (and vice-versa) in the wiring channel. This isolation typically improves the design of the integrated circuit by providing more reliable estimates of signal propagation in the wiring channels. <IMAGE>
申请公布号 EP0735584(A3) 申请公布日期 1997.12.29
申请号 EP19960301889 申请日期 1996.03.20
申请人 AT&T CORP. 发明人 FREYMAN, RONALD LAMAR;PEKARICH, STEVEN PAUL;MARTIN, TED R.
分类号 H05K1/02;H01L23/528;(IPC1-7):H01L23/528 主分类号 H05K1/02
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