Low power semiconductor memory device

摘要

A low power semiconductor memory device for minimizing power consumption is disclosed. The low power semiconductor memory device includes a memory cell array with a plurality of memory cells connected to a pair of bit lines, and having first and second pairs of data lines each having a normal data line and a complementary data line. The device further includes a first switching circuit for switch-connecting the pair of bit lines to the first pair of data lines in response to column select information and a sense amplifier connected to the pair of bit lines within the memory cell array. A driving circuit transfers external data to one of the normal data line and the complementary data line of the second pair of data lines in response to a write master signal. A data transfer circuit respectively transfers a signal of the normal data line of the second pair of data lines and an inverted signal thereof to the normal data line and the complementary data line of the first pair of data lines in response to the input of the write master signal.