Programmable frequency synthesizer having low phase noise sensitivity

摘要

The synthesiser has a phase detector (PHD) with a timer circuit (TMP) which has an active state during the counting cycle time equal to the product of the output period of the synthesiser and a first digital value (Ref1). A counter circuit (CD) has an output incremented by one each clock cycle (Ck) when the input to the synthesiser (Sin) is in an active state. A comparator (SUB1) compares the counter output with a second digital value (Ref2) and as a result generates a control signal (Cs) via a low pass filter (LPF) to adjust the output frequency of a voltage controlled oscillator (OSC). The counter is reset when the end of cycle signal (Ecy) is in the active state.