发明名称 Current mirror circuit and signal processing circuit having improved resistance to current output terminal voltage variation
摘要 A current mirror circuit includes a current input terminal; a first FET and a second FET, each having a gate terminal, a drain terminal, and a source terminal, the gate terminal of the first FET being connected to the gate terminal of the second FET; a third FET having a source terminal connected to the drain terminal of the first FET, and a drain terminal and a gate terminal connected to each other and to the current input terminal; and a fourth FET having a source terminal connected to the drain terminal of the second FET, a gate terminal connected to the gate terminal of the third FET, and a drain terminal serving as a current output terminal. Therefore, even when the output voltage varies, since the current is almost constant, the circuit is not adversely affected by the variation in the output voltage. As a result, error in the output current in response to variations in the output voltage is significantly reduced.
申请公布号 US5781061(A) 申请公布日期 1998.07.14
申请号 US19960696093 申请日期 1996.08.13
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 MIYASHITA, MIYO;YAMAMOTO, KAZUYA
分类号 G05F3/26;H03F3/343;H03K19/0175;H03K19/0944;(IPC1-7):G05F3/02 主分类号 G05F3/26
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