| 摘要 |
A method of forming DRAM circuitry includes, a) defining a memory array area on a substrate for formation of first conductivity type DRAM field effect transistors and defining an area peripheral to the array on the substrate for formation of second conductivity type transistors; b) providing a plurality of patterned gate lines within the array area and the peripheral area, the gate lines defining respective source areas and drain areas adjacent thereto; c) providing capacitor storage nodes over selected array source areas; d) providing a capacitor dielectric layer and an electrically conductive capacitor cell plate layer over the storage nodes and the peripheral area; and e) in two separate photomasking and two separate etching steps, etching the cell plate layer to substantially remove cell plate material from the peripheral area and provide bit line contact openings through the cell plate layer to selected drains in the array area. The method further includes, in two separate photomasking and two separate etching steps, collectively a) etching the capacitor cell plate layer to substantially remove cell plate material from the NMOS peripheral area and thereafter doping the NMOS peripheral area with n-type material, and b) etching the capacitor cell plate layer to substantially remove cell plate material from the PMOS peripheral area and thereafter doping the PMOS peripheral area with p-type material.
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