| 摘要 |
A CPU of a computer system utilizing a VLIW architecture comprises an instruction register, an instruction sequencing unit, a bank of data registers, a set of arithmetic/logic units (ALUs), and instruction decode logic. The bit positions in the instruction register correspond to a set of parcels or fields, each parcel corresponding to a different respective one of the ALUs. The operation, if any, performed by each ALU during a machine cycle is specified by the parcel corresponding to the ALU. Each parcel of an instruction may contain such information as an operation code (op code), source and destination registers, special registers, immediate data, storage addresses, etc. In order to reduce the total number of bits required to store an instruction, at least some of the bit positions required to specify such information to the instruction decode logic are implied by the position of the parcel within the instruction word. Preferably, multiple-way conditional branches may be specified in each instruction word. A variable number of conditional branches may be specified by using some of the parcels which would otherwise be available to specify operations in the ALUs.
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