AMPLIFIER WITH REDUCED INPUT CAPACITANCE

摘要

A JFET preamplifier for use with a high impedance transducer, having an inherently capacitive input bias impedance. The capacitance of the input bias im pedance is effectively neutralized by capacitively coupling the JFET gate bias circuit t o the source electrode of the JFET. The JFET preamplifier is configured as a source fo llower which reduces any capacitance between the JFET gate and source electrode by the open loop gain of the amplifier. By capacitively coupling the JFET gate bias circuit capacitance to the JFET source electrode, the overall input capacitance of the preamplifier stage is reduced.