POWER FET DEVICE

摘要

A power FET device comprising a semiconductor wafer substrate defining first and second surfaces, a gate electrode extending over the first surface of the substrate but insulated therefrom, and a drain electrode extending over the second surface of the substrate. The gate electrode defines a regular array of apertures. An FET body region of a first conductivity type is formed in the first surface of the substrate beneath each gate electrode aperture, each body region extending a first predetermined lateral distanc e from edges of the gate electrode defining the aperture. An FET source region of a second conductivity type is formed within the body region beneath each gate electrode aperture, each FET source region extending from the edges of the gate electrode defining the respective aperture a second predetermined lateral distance w hich is less than the first distance. A source electrode interconnects source contacts centrally located beneath each of the gate electrode apertures. An FET channel region is defined around the periphery of each source region. Pairs of adjacent gate electrode apertures define therebetween a strip of gate electrode the width of which varies along the length of the strip between a minimum which is substantially less than twice the first distance and a maximum which is substantially greater than twice the first distance. As a result, body dopant introduced through adjacent gate electrode apertures merges to form a single body structure extending continuously between the apertures beneath portions of the strip of gate electrode of minimum width.