发明名称 Fabrication method for chip size semiconductor package
摘要 A fabrication method for a chip size semiconductor package includes the steps of bonding conductive wires on bonding pads formed on an upper surface of a semiconductor chip, putting the semiconductor chip including the bonded conductive wires in an electrolyzer containing an electrolytic solution in such a manner that one end of each of the conductive wires is exposed outside of the electrolytic solution, attaching a plating electrode to an inner wall of the electrolyzer, attaching a conductive plate to serve as a common electrode to the exposed one end of each of the conductive wires; and connecting the conductive plate and the outer wall of the electrolyzer to an electric current source.
申请公布号 US5863816(A) 申请公布日期 1999.01.26
申请号 US19970937511 申请日期 1997.09.25
申请人 LG SEMICON CO., LTD. 发明人 CHO, JAE-WEON
分类号 C25D5/12;C25D7/12;H01L21/56;H01L21/60;H01L23/48;H01L23/50;(IPC1-7):H01L21/326;H01L21/479 主分类号 C25D5/12
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