发明名称 ECL LOGIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide an ECL logic circuit high in operating speed and capable of increasing output amplitude level to the degree without causing hindrance practically by connecting resistors between bases of differential bipolar transistor to be impressed with input signal, a load transistor connected to a collector of the differential bipolar transister and the loading transistor and a power source. SOLUTION: The AC output amplitudeΔVout(AC) in an output terminal Out 3 when an AC signal is inputted is calculated by formula I. In the formula 1, hfe is the AC amplifying rate of the transistor Q7. The AC amplifying rate hfe is increased so that AC output amplitudeΔVout(AC) is increased. Besides, AC output amplitudeΔVout(AC) is reduced by the term of hfe/hFE by formula II and the second term is subtracted by the hfe so that actual value load resistance R(AC) is drastically reduced. Therefore, high speed conversion is obtained in a collector response time and the high speed function of and ECL logical circuit is improved without reducing a circuit gain.
申请公布号 JPH1188148(A) 申请公布日期 1999.03.30
申请号 JP19970238627 申请日期 1997.09.03
申请人 NEC YAMAGATA LTD 发明人 KONDO TOYOO
分类号 H03K19/086;(IPC1-7):H03K19/086 主分类号 H03K19/086
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