发明名称 DATA REPRODUCTION DEVICE
摘要 PROBLEM TO BE SOLVED: To read both a PI series and a PO series at a high speed even in the case of using a DRAM by mapping data in a memory so that data after demodulation are read from each of pluralities of memory banks in the unit of a prescribed data amount. SOLUTION: It is required to store data from a data input circuit 7 to a memory at once for error correction. In this case, an address conversion circuit 5 converts a 1st address signal generated by an address generating circuit 4 into a 2nd address signal. Furthermore, the circuit 5 outputs a bank switching signal to allocate data in the memory to select a bank for each PI series in the order of the PI series. Thus, the PI series has consecutive addresses of the same bank and then is read at a high speed by selecting a long burst length. Furthermore, the PO series has discontinuous addresses, but since the same bank is not employed for the PO series, data are read at a high speed by selecting the bank at error correction.
申请公布号 JPH1198462(A) 申请公布日期 1999.04.09
申请号 JP19970254645 申请日期 1997.09.19
申请人 HITACHI LTD 发明人 HIRABAYASHI MASAYUKI;NAGAI YUTAKA;TAKEUCHI TOSHIFUMI
分类号 H04N5/92;G06F11/10;G11B20/10;G11B20/18;G11C7/10;G11C7/24;H03M13/00;H03M13/29;(IPC1-7):H04N5/92 主分类号 H04N5/92
代理机构 代理人
主权项
地址