| 摘要 |
PROBLEM TO BE SOLVED: To prevent the parasitic capacitance of a semiconductor device from increasing, even when a dummy pattern is used and eliminate the increase in the number of pattern correcting times which increases due to the existence of the dummy pattern. SOLUTION: A semiconductor device is provided with wirings formed on a semiconductor substrate and an inter-layer insulating film which is formed on the entire surface of the semiconductor substrate carrying the wiring and has a planarized upper surface. The wiring has a dummy pattern 5 which is formed so that the distance between the pattern 5 and a line 4 used as a signal line becomes 3-200μm. When the wiring interval is set to >=3μm, the parasitic capacitance of the semiconductor device can be ignored, and the operating speed of the device does not become slower. In addition, since the dummy pattern 5 can sufficiently exert a planarizing effect, even if the pattern 5 is separated from the wiring pattern by about 200μm, the correction for the pattern 5 is not required, and the layout of the semiconductor device becomes easier even when the pattern of another layer is corrected.
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