发明名称 Programmable state machine employing a cache-like arrangement
摘要 The programmable state machine includes a tag entry array and a new state array. All permissible combinations of current states and input values are represented within the tag entry array. The corresponding new state, to be transitioned to for each combination of current states and input values, is stored in the new state array. The tag entry array receives the current state and the input signals and generates a hit signal identifying which of the tag entries corresponds to the current state and input value signals. The new state array outputs the corresponding new state, based upon the hit signal received. In one embodiment, the tag entry array is configured as a fully associative cache tag entry array. In another embodiment, the tag entry array is configured as a set associative cache array. To eliminate the need to redundantly store a single new state, that corresponds to a large number of different transitions, a compare under mask arrangement is provided. As an alternative, a default new state arrangement is provided which outputs a default new state if a miss is detected within the tag entry array.
申请公布号 US5905902(A) 申请公布日期 1999.05.18
申请号 US19950537155 申请日期 1995.09.28
申请人 INTEL CORPORATION 发明人 O'CONNOR, DENNIS
分类号 G05B19/042;G06F12/08;(IPC1-7):G06F13/00 主分类号 G05B19/042
代理机构 代理人
主权项
地址